1. Technical Field
The present invention generally relates to semiconductor devices and fabrication of semiconductor devices. More particularly, the present invention relates to the reducing or eliminating delamination of a metal gate of a FinFET device.
2. Background Information
The two principal approaches for forming semiconductor device gate structures have been gate-first and gate-last process approaches.
In a gate-first fabrication approach, a metal gate is provided over a gate dielectric, and then patterned and etched to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided. In the gate-last approach, a sacrificial (or dummy) gate material is provided, patterned and etched to define one or more sacrificial gates. The one or more sacrificial gates are subsequently replaced with corresponding replacement metal gates, after source and drain features of the devices have been formed. The sacrificial gate material, such as, for example, amorphous silicon (a-Si) or polycrystalline silicon, holds the position for the subsequent metal gate to be formed. For instance, an amorphous silicon (a-Si) or polysilicon sacrificial gate material may be patterned and used during initial processing until high-temperature annealing to activate the source and drain features has been completed. Subsequently, the a-Si or polysilicon may be removed and replaced with the final metal gate.
Low resistance metal gate materials, such as tungsten, are currently employed due to advantages associated such as reduced gate contact resistance, which provide faster device performance. However, the poor adhesion between the layers during fabrication of the metal gate can have negative consequences, such as bubbling, blistering, peeling and/or delamination at the interface between the layers. Bubbling, blistering or peeling degrades the electrical contact between the layers resulting in low yield and low reliability in devices. The susceptibility of a device to the negative effects of poor adhesion between layers increases as the area of contact between poorly adhering layers increases.
Hence, there is a need to reduce or eliminate delamination of a metal gate of a FinFET device.